(1) Field of the Invention
This invention relates to improved thin film transistors, more particularly to thin film field effect transistors, provided with dual gate electrodes, one of which has an offset. The invention also relates to methods of fabricating dual gate transistors.
(2) Description of Prior Art
Many different types of semiconductor devices that can store binary information, or data in terms of electric charges, have been developed and are at present used in various computer memories. The list includes, static memories, dynamic memories, read only memories and the like. Semiconductor device memories are widely used because they have the capability of high integration density, and are relatively inexpensive. Among these memories, the static type semiconductor memory has found wide application as a random access memory (RAM), because it can retain stored data without periodic refresh operations.
The static random access memory (SRAM) can be implemented by a large number of flip-flop circuits, each of which stores one bit of information. CMOS flip-flop circuits, each normally composed of a pair of N-channel MOS field effect transistors, and a pair of P-channel MOS field effect transistors, are widely utilized as memory cells because power consumption of the device is very low. However, initially CMOS flip-flop memories necessitated a relatively large area on a semiconductor substrate, making high integration density difficult to attain.
A general circuit structure of the CMOS type static memory cell may be understood by reference to U.S. Pat. No. 4,980,732 and is shown in FIG. 1. In FIG. 1, N-channel MOS transistors QN1, QN2 and P-channel MOS transistors QP1 and QP2 form a CMOS flip-flop circuit in which the transistors QP1 and QN1 having electrically common gates G1 form a first CMOS inverter, and the transistors QP2 and QN2 having electrically common gates G2 form a second CMOS inverter. Output nodes N1 and N2 of the first and second CMOS inverters are connected to a pair of digit lines DL and DL, via a pair of N-channel transfer gate transistors QN3 and QN4, controlled by a word line, WL.
In order to reduce the area that each CMOS circuit occupied on the device, it was proposed to form a pair of P-channel MOS transistors as thin film transistors (TFTS), such as silicon-on-insulator (SOI) structure, with the other pair of N-channel transistors formed in the body of the device. With this structure, the P-channel transistors can overlap a part of the N-channel MOS transistors, and therefore the integration scale of the SRAM is enlarged.
An example of how a thin film transistor is embodied in a CMOS structure is illustrated in FIG. 2. In FIG. 2, a P-type silicon substrate 10 is overlaid with a gate insulator film 16, on which a gate electrode 14 of polycrystalline silicon is formed. In silicon substrate 10 on both sides of the gate electrode 14, N-type diffused regions 14A and 14B at an impurity concentration of between 10.sup.20 and 10.sup.21 Cm.sup.-3 are formed as source and drain regions of transistor QN1. The gate electrode 14 and the N-type diffused regions 14A, 14B constitute the N-channel transistor QN1 in FIG. 1. Accordingly, the N-type diffused region 14A is connected to the ground potential. In FIG. 2, a gate insulator film 17 is formed on the gate electrode 14, and an N-type silicon thin film 13 is formed on the gate insulator films 16 and 17. P-type diffused region 13S and 13D of an impurity concentration of between 10.sup.19 and 10.sup.21 Cm.sup.-3 are formed in the ports of the silicon thin film 13 on both the sides of the gate electrode 14, and the P-channel transistor QP1 in FIG. 1 is formed by the SOI structure by the gate electrode 14 and the P-type diffused regions 13S, 13D. The P-type diffused layer 13S is connected to power source potential Vcc by a lead out electrode 11 composed of aluminum. The P-type diffused layer 13D and the N-type diffused region 14B are connected by a conductive layer 18 of aluminum at node N1. Symbols 12A, 12B and 12C denote thick insulator films, and numeral 15 denotes a port of gate electrode G2 of the second inverter which is formed of P-channel transistor QP2 and N-channel transistor QN2 in FIG. 1.
However, the crystalline characteristics of the polycrystalline silicon film, or the monocrystalline silicon film formed on the semiconductor substrate over an insulating layer is not good, and a P-N junction formed in the silicon film is very leaky. Therefore, power consumption, that is standby current of the SRAM employing the aforementioned SOI type transistors, is relatively large.
A solution to reduce the leakage in a polycrystalline silicon layer of a thin film transistor is set forth in U.S. Pat. No. 4,980,732 and is illustrated in FIG. 3. In FIG. 3 the elements corresponding to the elements shown in FIG. 2 are denoted by the same reference numerals. Note that the P-N junction 20 between the channel region 13 and drain region 13D is spaced from the gate electrode 16. In contrast, corresponding P-N junction 19 in FIG. 2 is directly above gate electrode 16. This space between the channel and the drain reduces the Gate-induced Drain Leakage which is caused by the band-to-band tunneling in the gate overlap region of the drain.
As is believed apparent, the locating of the blocking mask for ion implanting the impurities into the polycrystalline film that forms the source and drain regions of the transistor is very exacting. The accuracy of defining the geometry of offset region is limited by the overlay accuracy of photo lithography process which could be large compared with its typical value.
FIG. 4 illustrates a modification of the structure shown in FIG. 3 as given in the U.S. Pat. No. 4,980,732. In FIG. 4 the elements corresponding to the elements shown in FIGS. 2 and 3 are denoted by the same reference numerals. FIG. 4 illustrates a different placement of the thin film P-channel transistor, i.e. over a thick oxide layer 16A. Gate electrode 19 is provided which is electrically connected to gate 14 of the N-channel transistor.
In such very small Thin Film Devices (TFT) with very short channel length, the leakage through the devices in the off state, presents formidable problems. This presents more of a problem, since the medium in the body of the transistor is polycrystalline silicon, as contrasted with monocrystalline silicon. Dual gate electrodes positioned on opposite sides of the polycrystalline layer are known and have materially increased the on current. But the dual gate without offset will still suffer from the large off current, because existence of large gate to drain electric field.
The use of a single gate electrode with an offset region in thin film transistors is also known and has been implemented to reduce the leakage in the off condition. This TFT structure is described in U.S. Pat. No. 4,980,732.
The offset could reduce the electric field between gate and drain and thus reduce the induced leakage current, which is also known as gate induced drain leakage (GIDL).
While the prior art recognizes the need to minimize or eliminate leakage current in thin film transistors, and has separately used the two aforedescribed structures to meet the objective, further reduction is very desirable.